[AMD] dsv4-fp4-mi355x-sglang: switch fixed-seq-len search space to TP4#1768
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…ter yaml Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…able isl=1024 and expand isl=8192 Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
… space update Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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functionstackx
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@seungrokj can u try looking into sgl mtp too? would switching it help? +viz @1am9trash
…dp-attn conc=512 point Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…oint for dsv4-fp4-mi355x-sglang Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…n and TP4 TP-only rows for isl=1024 and isl=8192 Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528680882 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528759942 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27528759942 |
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@functionstackx @cquil11 can you plz approve this ? |
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/reuse-sweep-run |
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/merge-prs |
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Cursor Bugbot has reviewed your changes and found 1 potential issue.
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Reviewed by Cursor Bugbot for commit b519ea6. Configure here.
| search-space: | ||
| - { tp: 8, dp-attn: true, conc-start: 64, conc-end: 2048 } | ||
| - { tp: 8, dp-attn: false, conc-start: 1 , conc-end: 32 } | ||
| - { tp: 4, dp-attn: true, conc-start: 16, conc-end: 128 } |
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TP4 dp-attn conc mismatch
Medium Severity
The new TP4 dp-attn: true fixed-seq-len rows use conc-start 16 and conc-end 128, but the same PR’s perf-changelog.yaml entry documents that sweep as concurrency 32–2048. The CI sweep will not cover the high-concurrency TP4 dp-attn range the changelog and PR describe.
Additional Locations (2)
Reviewed by Cursor Bugbot for commit b519ea6. Configure here.


Summary
dsv4-fp4-mi355x-sglangfixed-seq-len search space from TP8 to TP4 for bothisl=1024andisl=8192scenariosisl=8192coverage: add TP4 dp-attn sweep (conc 32–2048) alongside TP4 TP-only sweep (conc 1–32)perf-changelog.yamlwith change descriptionTest plan
dsv4-fp4-mi355x-sglangfixed-seq-len CI jobs launch with TP4 configs🤖 Generated with Claude Code
Note
Low Risk
YAML-only benchmark matrix changes; no serving or application code paths are modified, though CI will run different TP/concurrency combinations on MI355X.
Overview
Updates
dsv4-fp4-mi355x-sglangin.github/configs/amd-master.yamlso fixed-seq-len jobs emphasize TP4 alongside the existing TP8 + dp-attn high-concurrency row for both isl=1024 and isl=8192.For each scenario, the former TP8, dp-attn=false sweep (conc 1–32) is replaced by TP4 rows: dp-attn=true (conc 16–128) and dp-attn=false (conc 1–32). The TP8, dp-attn=true sweep (conc 64–2048) is unchanged.
Adds a
perf-changelog.yamlentry fordsv4-fp4-mi355x-sglangdescribing the TP4 search-space shift and expanded isl=8192 coverage.Reviewed by Cursor Bugbot for commit b519ea6. Bugbot is set up for automated code reviews on this repo. Configure here.